Burr-free digital delay chain

The invention discloses a burr-free digital delay chain, and belongs to the technical field of integrated circuit digital. The circuit comprises a configurable gating module, a clock gating module and a delay line formed by connecting multiple stages of delay units in series, wherein each delay unit consists of a delay circuit and a gating module. Link delay is realized by using a CMOS (complementary metal oxide semiconductor) process basic unit, the clock signal duty ratio is improved by adopting a structure of two completely symmetrical delay circuits and phase inverters, dynamic burr-free switching of a delay chain is realized through a burr-free switching circuit, the configurability of the delay chain is realized through a one-hot decoding gating circuit, and the dynamic burr-free switching of the delay chain is realized through the one-hot decoding gating circuit. And the dynamic power consumption of the circuit is reduced by adopting a clock dynamic gating design. According to the delay chain circuit,