Unified memory address translation

A unified memory address translation system includes a translation queue module configured to receive translation requests for different modes of real addresses (RAs) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for a previous request of the RA and provide the previous successful translation results to a translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation traversal address generation (UTWAG) module is configured to provide translation support for each of the different modes of translation requests. The memory interface is coupled between the UTWAG and the physical memory. 统一存储器地址转换系统包括转换队列模块，其被配置为接收针对物理存储器的真实地址(RA)的不同模式的转换请求。转换缓存(XLTC)接口被配置为接收针对RA的先前请求的成功的转换结果，并将先前成功的转换结果提供给转换队列模块。多个页表条目组(PTEG)搜索模块耦合到转换队列模块。统一转换遍历地址生成(UTWAG)模块被配置为针对不同模式的转换请求中的每个模式提供转换支持。存储器接口耦合在UTWAG与物理存储器之间。