Clock adjustment circuit and method

A clock adjustment circuit and a related clock adjustment method are provided. The clock adjustment circuit includes a pattern screening circuit, a phase error detector (PED) circuit, and a phase error calculation circuit. The pattern screening circuit is to select a first predetermined data pattern from a plurality of consecutive data samples in an acquisition mode of the clock adjustment circuit, wherein the plurality of consecutive data samples originate from an output of the first sampler circuit. The PED circuit is configured to detect a phase error based on an output of the pattern screening circuit and an error sample derived from an output of the second sampler circuit. A phase error calculation circuit is configured to determine a timing compensation for a sampling clock from an output of the PED circuit, wherein the sampling clock is used by the first sampler circuit and the second sampler circuit. 提供了一种时钟调整电路以及相关的时钟调整方法。时钟调整电路包括样式筛选电路、相位误差检测器(PED)电路和相位误差计算电路。样式筛选电路用于在时钟调整电路的获取模式下从多个连续数据样本中选择第一预定数据样