High-reliability chip packaging method and packaging structure

The invention discloses a high-reliability chip packaging method and structure, and the method comprises the following steps: completing wafer bonding and destressing thinning, etching a chute, preparing a passivation layer on the surface of a wafer, enabling the passivation layer to be good in adhesion uniformity on the side wall of the chute, and finally completing the redistribution of a circuit layer and a solder mask layer. And performing ball mounting and cutting to obtain a final finished product. According to the method, one-step photoetching and one-step etching are adopted, the technological process is simplified, the packaging cost is reduced, the packaging time is shortened, the technology is relatively simple, the inclined groove with the moderate and gentle groove angle and the large opening is formed through one-step silicon through hole etching, the passivation layer can be evenly attached to the side wall of the inclined groove, the electrical property failure risk is reduced, and the packagi