Anti-fuse structure, forming method thereof and memory
The invention relates to the technical field of semiconductors, and relates to an anti-fuse structure and a forming method thereof, and a memory, the anti-fuse structure comprises a substrate, a first oxide layer, an isolation layer, a second oxide layer, a first gate layer and a second gate layer,...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention relates to the technical field of semiconductors, and relates to an anti-fuse structure and a forming method thereof, and a memory, the anti-fuse structure comprises a substrate, a first oxide layer, an isolation layer, a second oxide layer, a first gate layer and a second gate layer, an active layer is formed on the substrate, and the active layer comprises a first channel region and a second channel region which are arranged at an interval; the first oxide layer covers the side wall of the active layer; the thickness of the first oxide layer on the side wall of the active layer of the first channel region is smaller than that of the first oxide layer on the side wall of the active layer of the second channel region; the isolation layer is located on one side, away from the active layer, of the first oxide layer; the second oxide layer is located on the side, away from the first oxide layer, of the isolation layer; the first gate layer is located at the top of the active layer of the first chan |
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