Clock generation circuit, equidistant four-phase signal generation method and memory

The invention relates to the field of semiconductor circuit design, in particular to a clock generation circuit, an equidistant four-phase signal generation method and a memory, and the clock generation circuit comprises a four-phase clock generation circuit which is used for receiving an internal clock signal and a complementary clock signal of the memory to which the clock generation circuit belongs, the clock generator is configured to generate a first clock signal, a second clock signal, a third clock signal and a fourth clock signal with the same period; the signal delay circuit is configured to perform signal delay on a first clock signal, a second clock signal, a third clock signal and a fourth clock signal based on a delay command, and the delays of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are different; the signal loading circuit is used for generating a first indication signal and a second indication signal; and the test circuit is used for