Ultra-low power immediate lock phase locked loop (PLL)

Systems and methods reduce the locking time of a Type II all digital phase locked loop (ADPLL) circuit by performing steps including: receiving a reference signal having a reference frequency; and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference freque...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	CHOU CHIACHEN, HUNG CHENG-HSIEN, HSU CHIH-WEI
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRICITY
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