Ultra-low power immediate lock phase locked loop (PLL)

Systems and methods reduce the locking time of a Type II all digital phase locked loop (ADPLL) circuit by performing steps including: receiving a reference signal having a reference frequency; and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal for generating a feedback signal. Determining an initial phase difference between the reference signal and the feedback signal using a time-to-digital converter; and a digital initial phase compensation circuit adjusts the initial phase difference to a phase difference that is substantially zero to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady state condition over ten or less cycles of the reference signal. 系统和方法通过执行步骤减少II型全数字锁相环(ADPLL)电路的锁定时间，这些步骤包括：接收具有参考频率的参考信号；以及将数控振荡器(DCO)设置为大于该参考频率的目标频率。该DCO生成用于生成反馈信号的输出信号。使用时间到数字转换器确定该参考信号与该反馈信号之间的初始相位差；以及数字初始相位补偿电路将该初始相位差调整到基本上为零的相位差以减少该ADPLL电路的锁定时间，使得该ADPLL电路在该参考信号的十个或更少的循环内到达稳态状况。