SEMICONDUCTOR DEVICE AND MOTOR DRIVING SYSTEM

Embodiments provide a semiconductor device and a motor driving system capable of suppressing cost. According to one embodiment, a semiconductor device includes first to fifth terminals, an amplifier circuit, and a switching section. The first terminal (P1) is connected to a first end of a first resi...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	KOBAYASHI KAZUYA, ODAWARA HIROSHI
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	AMPLIFIERS APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS BASIC ELECTRONIC CIRCUITRY CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORSOR DYNAMO-ELECTRIC CONVERTERS CONTROL OR REGULATION THEREOF CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRICITY GENERATION MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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Beschreibung
Zusammenfassung:	Embodiments provide a semiconductor device and a motor driving system capable of suppressing cost. According to one embodiment, a semiconductor device includes first to fifth terminals, an amplifier circuit, and a switching section. The first terminal (P1) is connected to a first end of a first resistor provided to the outside. A second terminal (P2) is connected to a second end of the first resistor. The third terminal (P3) is connected to a first end of a second resistor provided to the outside. A second terminal of the second resistor is connected to a fourth terminal (P4). The amplifier circuit has a first input terminal, a second input terminal, and an output terminal. An output terminal of the amplifier circuit is connected to a fifth terminal (P9). The switching unit is configured to switch between a first state in which the first input terminal is connected to the first terminal (P1) and the second input terminal is connected to the second terminal (P2), and a second state in which the first input ter