FPGA data acceleration method based on high parallel scene

The invention discloses an FPGA (Field Programmable Gate Array) data acceleration method based on a high parallel scene, which comprises the following steps: establishing a binary tree for comparison, assuming that the number of leaf nodes of the tree is N, setting a global flag bit for the binary t...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	LIU HUILIN, CHEN YONGZHENG, QIAO BAIYOU, YIN SHUAIBO, ZHANG LAN, HAN DONGHONG, TANG LICHEN, WU GANG
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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