FPGA data acceleration method based on high parallel scene

The invention discloses an FPGA (Field Programmable Gate Array) data acceleration method based on a high parallel scene, which comprises the following steps: establishing a binary tree for comparison, assuming that the number of leaf nodes of the tree is N, setting a global flag bit for the binary tree, and setting a flag bit for each non-leaf node of the binary tree; sequentially inserting data to be processed into empty leaf nodes of the binary tree, comparing at non-leaf nodes, transmitting smaller data in comparison into a father node to continue to participate in comparison, finally outputting the minimum data in the binary tree, and emptying the leaf node where the minimum data is located. Updating the global flag bit according to the flag bit of the output data; inserting new data, setting a flag bit of the new data, comparing the data in the tree, and outputting the minimum data after the comparison; according to the method and the device, the sorted data volume in unit time is increased, the running