Integrated circuit

An integrated circuit according to an embodiment of the present invention is provided with: a plurality of AD conversion circuits including a first AD conversion circuit and a second AD conversion circuit; and a control circuit that, in order to prevent the first AD conversion circuit from being affected by noise generated by the sampling process (S2) of the second AD conversion circuit, delays the start timing than the normal start timing in the sampling process of the second AD conversion circuit, but shortens the sampling time, thereby reducing the start timing of the sampling process of the second AD conversion circuit in order to prevent the first AD conversion circuit from being affected by noise generated by the sampling process (S2) of the second AD conversion circuit. The end timing of the sampling process of the second AD conversion circuit is controlled so as to be the same as the end timing when the normal sampling process is performed. 本发明的实施方式涉及一种集成电路，具备：多个AD转换电路，包括第一AD转换电路和第二AD转换电路；以及控制电路，为了使上述