On-chip jig de-embedding test method and device
The invention provides an on-chip clamp de-embedding test method comprising the following steps: providing a de-embedding test structure comprising an integral structure, a first transmission line structure and a second transmission line structure which are mutually independent; wherein the overall...
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| creator | JIAO MINGQI ZHANG SHENGLI XIE LIANG TANG FUSHENG LYU SHIRONG |
| description | The invention provides an on-chip clamp de-embedding test method comprising the following steps: providing a de-embedding test structure comprising an integral structure, a first transmission line structure and a second transmission line structure which are mutually independent; wherein the overall structure comprises a to-be-tested device, and the length of the second transmission line structure is twice that of the first transmission line structure; respectively testing the overall structure, the first transmission line structure and the second transmission line structure to obtain a scattering parameter, a first scattering parameter and a second scattering parameter of the overall structure; performing matrix operation to obtain parasitic parameters to be de-embedded; and performing de-embedding operation according to the scattering parameter and the parasitic parameter of the overall structure to obtain the intrinsic scattering parameter of the to-be-tested device. According to the invention, the ideal th |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN116794351A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN116794351A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN116794351A3</originalsourceid><addsrcrecordid>eNrjZND3z9NNzsgsUMjKTFdISdVNzU1KTUnJzEtXKEktLlHITS3JyE9RSMxLAUqWZSan8jCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSSeGc_Q0Mzc0sTY1NDR2Ni1AAAzFEqIQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>On-chip jig de-embedding test method and device</title><source>esp@cenet</source><creator>JIAO MINGQI ; ZHANG SHENGLI ; XIE LIANG ; TANG FUSHENG ; LYU SHIRONG</creator><creatorcontrib>JIAO MINGQI ; ZHANG SHENGLI ; XIE LIANG ; TANG FUSHENG ; LYU SHIRONG</creatorcontrib><description>The invention provides an on-chip clamp de-embedding test method comprising the following steps: providing a de-embedding test structure comprising an integral structure, a first transmission line structure and a second transmission line structure which are mutually independent; wherein the overall structure comprises a to-be-tested device, and the length of the second transmission line structure is twice that of the first transmission line structure; respectively testing the overall structure, the first transmission line structure and the second transmission line structure to obtain a scattering parameter, a first scattering parameter and a second scattering parameter of the overall structure; performing matrix operation to obtain parasitic parameters to be de-embedded; and performing de-embedding operation according to the scattering parameter and the parasitic parameter of the overall structure to obtain the intrinsic scattering parameter of the to-be-tested device. According to the invention, the ideal th</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230922&DB=EPODOC&CC=CN&NR=116794351A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25566,76549</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230922&DB=EPODOC&CC=CN&NR=116794351A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JIAO MINGQI</creatorcontrib><creatorcontrib>ZHANG SHENGLI</creatorcontrib><creatorcontrib>XIE LIANG</creatorcontrib><creatorcontrib>TANG FUSHENG</creatorcontrib><creatorcontrib>LYU SHIRONG</creatorcontrib><title>On-chip jig de-embedding test method and device</title><description>The invention provides an on-chip clamp de-embedding test method comprising the following steps: providing a de-embedding test structure comprising an integral structure, a first transmission line structure and a second transmission line structure which are mutually independent; wherein the overall structure comprises a to-be-tested device, and the length of the second transmission line structure is twice that of the first transmission line structure; respectively testing the overall structure, the first transmission line structure and the second transmission line structure to obtain a scattering parameter, a first scattering parameter and a second scattering parameter of the overall structure; performing matrix operation to obtain parasitic parameters to be de-embedded; and performing de-embedding operation according to the scattering parameter and the parasitic parameter of the overall structure to obtain the intrinsic scattering parameter of the to-be-tested device. According to the invention, the ideal th</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND3z9NNzsgsUMjKTFdISdVNzU1KTUnJzEtXKEktLlHITS3JyE9RSMxLAUqWZSan8jCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSSeGc_Q0Mzc0sTY1NDR2Ni1AAAzFEqIQ</recordid><startdate>20230922</startdate><enddate>20230922</enddate><creator>JIAO MINGQI</creator><creator>ZHANG SHENGLI</creator><creator>XIE LIANG</creator><creator>TANG FUSHENG</creator><creator>LYU SHIRONG</creator><scope>EVB</scope></search><sort><creationdate>20230922</creationdate><title>On-chip jig de-embedding test method and device</title><author>JIAO MINGQI ; ZHANG SHENGLI ; XIE LIANG ; TANG FUSHENG ; LYU SHIRONG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN116794351A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>JIAO MINGQI</creatorcontrib><creatorcontrib>ZHANG SHENGLI</creatorcontrib><creatorcontrib>XIE LIANG</creatorcontrib><creatorcontrib>TANG FUSHENG</creatorcontrib><creatorcontrib>LYU SHIRONG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JIAO MINGQI</au><au>ZHANG SHENGLI</au><au>XIE LIANG</au><au>TANG FUSHENG</au><au>LYU SHIRONG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>On-chip jig de-embedding test method and device</title><date>2023-09-22</date><risdate>2023</risdate><abstract>The invention provides an on-chip clamp de-embedding test method comprising the following steps: providing a de-embedding test structure comprising an integral structure, a first transmission line structure and a second transmission line structure which are mutually independent; wherein the overall structure comprises a to-be-tested device, and the length of the second transmission line structure is twice that of the first transmission line structure; respectively testing the overall structure, the first transmission line structure and the second transmission line structure to obtain a scattering parameter, a first scattering parameter and a second scattering parameter of the overall structure; performing matrix operation to obtain parasitic parameters to be de-embedded; and performing de-embedding operation according to the scattering parameter and the parasitic parameter of the overall structure to obtain the intrinsic scattering parameter of the to-be-tested device. According to the invention, the ideal th</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING |
| title | On-chip jig de-embedding test method and device |
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