On-chip jig de-embedding test method and device
The invention provides an on-chip clamp de-embedding test method comprising the following steps: providing a de-embedding test structure comprising an integral structure, a first transmission line structure and a second transmission line structure which are mutually independent; wherein the overall...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention provides an on-chip clamp de-embedding test method comprising the following steps: providing a de-embedding test structure comprising an integral structure, a first transmission line structure and a second transmission line structure which are mutually independent; wherein the overall structure comprises a to-be-tested device, and the length of the second transmission line structure is twice that of the first transmission line structure; respectively testing the overall structure, the first transmission line structure and the second transmission line structure to obtain a scattering parameter, a first scattering parameter and a second scattering parameter of the overall structure; performing matrix operation to obtain parasitic parameters to be de-embedded; and performing de-embedding operation according to the scattering parameter and the parasitic parameter of the overall structure to obtain the intrinsic scattering parameter of the to-be-tested device. According to the invention, the ideal th |
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