Wafer-level multi-GPU simulation method and device based on Gem5 framework and storage medium
The invention discloses a multi-GPU (Graphics Processing Unit) analogue simulation method based on a Gem5 framework, which is used for a wafer-level system and comprises the following steps of: building a Gem5 system simulation running environment, downloading a source file, compiling and running; t...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention discloses a multi-GPU (Graphics Processing Unit) analogue simulation method based on a Gem5 framework, which is used for a wafer-level system and comprises the following steps of: building a Gem5 system simulation running environment, downloading a source file, compiling and running; the method comprises the following steps: creating a plurality of GPU components, respectively connecting L2 caches of a plurality of GPUs to a Directory, and respectively pointing the L2 caches to memory segments to which the GPUs belong by the Directory; the ROCk driver is changed, a plurality of software queues are created for one or more programs, the software queues are distributed to a plurality of GPUs, and a doorbell region is created for each GPU; and carrying out simulation test on the wafer-level system of the multiple GPUs by adopting the built Gem5 system, and verifying the system performance. Therefore, communication, interaction and scheduling among multiple GPUs are realized, so that the design time |
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