MULTIPLICATION ARRAY

The invention provides a data processing device. The AxB multiplier array has a set of logic gates clocked by a first clock signal, where both A and B are integers. A CxD multiplier array separate from the AxB multiplier array has a second set of logic gates clocked by a second clock signal, where both C and D are integers. A summing circuit performs an addition operation between a first at least partial product generated by the AxB multiplier array and a second at least partial product generated by the CxD multiplier array. 本发明提供了一种数据处理装置。AxB乘法器阵列具有由第一时钟信号计时的一组逻辑门，其中A和B两者均为整数。与该AxB乘法器阵列分开的CxD乘法器阵列具有由第二时钟信号计时的第二组逻辑门，其中C和D两者均为整数。加法电路在由该AxB乘法器阵列产生的第一至少部分乘积与由该CxD乘法器阵列产生的第二至少部分乘积之间执行加法运算。