Multiphase clock generation circuit

A multiphase clock generation circuit is used for generating multiphase non-overlapping clock signals. The multiphase clock generation circuit comprises a loop structure and a plurality of latches (NOR21, NOR22, NOR23, NOR24, NOR25, NOR26, NOR27 and NOR28), wherein the loop structure is formed by electrically connecting the input ends and the output ends of a plurality of logic gates (G11, G12, G13, G14, G15, G16, G17 and G18) end to end; the latches are used for latching signals of the input ends of the logic gates; the multiphase clock generation circuit performs logical operation according to selection signals and clock signals received by the plurality of logic gates (G11, G12, G13, G14, G15, G16, G17, G18), latches (NOR21, NOR22, NOR23, NOR24, NOR25, NOR26, NOR27, NOR28) are used for latching data of the upper-level logic gate received by the logic gates in the loop, and multiphase non-overlapping clock signals are output through the output ends of the plurality of logic gates. From the input end to the