Test structure of wafer-level system and operation method thereof

A test structure of a wafer level system controls TAPs of dies in a wafer through a TAP controller to form a two-dimensional test network, where each die includes a first test access port TAP, a second test access port TAP, and a third test access port TAP. The first TAP is in communication connection with the third TAP in the upper-level crystal grain in the Y direction to form a Y-direction test chain, the second TAP is in communication connection with the third TAP in the lower-level crystal grain in the X direction to form an X-direction test chain, and the third TAP can be configured to be in communication connection with the first TAP in the Y direction or in communication connection with the second TAP in the X direction according to requirements. And a complete test chain is formed. According to the two-dimensional grid deployment, when the test structure has a production defect, the function test of the crystal grain can be effectively carried out, the yield is further improved, in addition, a Y-dire