Delay and bit width variable pipelined cache data caching method and device

The invention discloses a pipelined cache data caching method and device with variable delay and bit width, and the method comprises the steps: S01, when a caching request is received, caching the request in buffers corresponding to a plurality of data array groups in a pipelined manner, and generating a read-write micro request for accessing each data array group in a pipelined manner by changing the information in the request; s02, determining the number of data array groups and the number of RAMs according to the configured flow line width and cache data block width; and S03, when each data array group is accessed, accessing each data array group to request a flow to enter the register and be transmitted to the next station, obtaining the number of registers accessed by the RAM in multiple cycles, and selecting requests in the register consistent with the currently configured RAM in multiple cycle delay beats. According to the method, the pipelined cache data with variable delay and variable bit width can