High-speed delay-locked loop with wide frequency locking range and locking method thereof
The invention discloses a high-speed delay phase-locked loop with a wide frequency locking range and a locking method of the high-speed delay phase-locked loop, and belongs to the field of integrated circuit design. The voltage-controlled delay chain is used for generating nine paths of eight-phase...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention discloses a high-speed delay phase-locked loop with a wide frequency locking range and a locking method of the high-speed delay phase-locked loop, and belongs to the field of integrated circuit design. The voltage-controlled delay chain is used for generating nine paths of eight-phase differential clock signals; the logic level converter is used for generating nine paths of eight-phase single-ended clock signals; the error lock detection module is used for generating a voltage regulation signal according to the comparison of the total delay of the voltage-controlled delay chain and a reference clock period; the phase detection module is used for adjusting the total delay of the voltage-controlled delay chain according to the voltage adjusting signal, and adjusting the control voltage value according to the comparison result of the phase difference of the reference clock and the feedback clock after the phase detection module enters a normal working state so as to adjust the total delay of the vo |
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