Power transistor with terminal trench in terminal reduced surface field region

The invention relates to a power transistor with terminal trenches in terminal reduced surface electric field regions. An apparatus (100) includes a transistor formed on a substrate (302). The transistor includes an n-type drain contact layer (312), an n-type drain layer (314), an oxide layer (332), a p-type body region (324), a p-type terminal region (322), a body trench (110), and a terminal trench (122). The n-type drain contact layer is proximate a bottom surface (306) of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. And the oxide layer is externally connected with a transistor region (102). The p-type body region is positioned within the transistor region. The p-type terminal region extends from below the oxide layer to an edge of the transistor region, thereby forming a continuous junction with the p-type body region. The body trench is within the transistor region and interleaved with the p-type body region, whereas the terminal trench is outside the transistor