Processor instruction set architecture for machine learning with low-bit precision weights

The invention discloses a processor instruction set architecture for machine learning with low bit precision weights. A technique for controlling a processing device. The technique includes receiving an input feature value (514) from a first register (420). The technique further includes receiving a weight value (510) from a second register (424). The technique further includes receiving a first address of an output register (520, 522). The technique further includes performing a matrix multiplication of the input feature value and the weight value in parallel to obtain a matrix multiplication result. The technique further includes providing the matrix multiplication result to the output register. 本发明公开了具有低位精度权重的用于机器学习的处理器指令集架构。一种用于控制处理设备的技术。所述技术包括从第一寄存器(420)接收输入特征值(514)。所述技术还包括从第二寄存器(424)接收权重值(510)。所述技术还包括接收输出寄存器(520,522)的第一地址。所述技术还包括并行执行所述输入特征值和权重值的矩阵乘法以获得矩阵乘法结果。所述技术还包括向所述输出寄存器提供所述矩阵乘法结果。