Network-based multi-FPGA debugging system and method
The invention relates to a network-based multi-FPGA (Field Programmable Gate Array) debugging system, which comprises a PC (Personal Computer) end, server software, a network switch and a plurality of FPGA boards with network ports, according to the method, a traditional field debugging method for t...
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creator | ZHOU DONGLAI WANG JING HU CONG ZHU ZHENG YANG ZHENJIA ZHENG FEI ZUO WENCUI |
description | The invention relates to a network-based multi-FPGA (Field Programmable Gate Array) debugging system, which comprises a PC (Personal Computer) end, server software, a network switch and a plurality of FPGA boards with network ports, according to the method, a traditional field debugging method for the target FPGA board system is networked, so that debugging personnel can remotely debug and maintain the target FPGA board-level system through the Internet, the development and debugging efficiency is improved, and the maintenance cost is reduced. Program programming and debugging are carried out by adopting a network cable or an optical fiber, the limitation of the length of a JTAG cable is broken through, the JTAG cable needs to be connected with a PC, a special working scene can be applicable only by connecting a network and a network switch, the method is simple and low in maintenance cost, point-to-point debugging and analysis are supported, and many-to-many batch debugging and analysis are also supported. A |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN116662175A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN116662175A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN116662175A3</originalsourceid><addsrcrecordid>eNrjZDDxSy0pzy_K1k1KLE5NUcgtzSnJ1HULcHdUSElNKk1Pz8xLVyiuLC5JzVVIzAPKp5Zk5KfwMLCmJeYUp_JCaW4GRTfXEGcP3dSC_PjU4oLE5NS81JJ4Zz9DQzMzMyNDc1NHY2LUAAD6iyxS</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Network-based multi-FPGA debugging system and method</title><source>esp@cenet</source><creator>ZHOU DONGLAI ; WANG JING ; HU CONG ; ZHU ZHENG ; YANG ZHENJIA ; ZHENG FEI ; ZUO WENCUI</creator><creatorcontrib>ZHOU DONGLAI ; WANG JING ; HU CONG ; ZHU ZHENG ; YANG ZHENJIA ; ZHENG FEI ; ZUO WENCUI</creatorcontrib><description>The invention relates to a network-based multi-FPGA (Field Programmable Gate Array) debugging system, which comprises a PC (Personal Computer) end, server software, a network switch and a plurality of FPGA boards with network ports, according to the method, a traditional field debugging method for the target FPGA board system is networked, so that debugging personnel can remotely debug and maintain the target FPGA board-level system through the Internet, the development and debugging efficiency is improved, and the maintenance cost is reduced. Program programming and debugging are carried out by adopting a network cable or an optical fiber, the limitation of the length of a JTAG cable is broken through, the JTAG cable needs to be connected with a PC, a special working scene can be applicable only by connecting a network and a network switch, the method is simple and low in maintenance cost, point-to-point debugging and analysis are supported, and many-to-many batch debugging and analysis are also supported. A</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230829&DB=EPODOC&CC=CN&NR=116662175A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230829&DB=EPODOC&CC=CN&NR=116662175A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ZHOU DONGLAI</creatorcontrib><creatorcontrib>WANG JING</creatorcontrib><creatorcontrib>HU CONG</creatorcontrib><creatorcontrib>ZHU ZHENG</creatorcontrib><creatorcontrib>YANG ZHENJIA</creatorcontrib><creatorcontrib>ZHENG FEI</creatorcontrib><creatorcontrib>ZUO WENCUI</creatorcontrib><title>Network-based multi-FPGA debugging system and method</title><description>The invention relates to a network-based multi-FPGA (Field Programmable Gate Array) debugging system, which comprises a PC (Personal Computer) end, server software, a network switch and a plurality of FPGA boards with network ports, according to the method, a traditional field debugging method for the target FPGA board system is networked, so that debugging personnel can remotely debug and maintain the target FPGA board-level system through the Internet, the development and debugging efficiency is improved, and the maintenance cost is reduced. Program programming and debugging are carried out by adopting a network cable or an optical fiber, the limitation of the length of a JTAG cable is broken through, the JTAG cable needs to be connected with a PC, a special working scene can be applicable only by connecting a network and a network switch, the method is simple and low in maintenance cost, point-to-point debugging and analysis are supported, and many-to-many batch debugging and analysis are also supported. A</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDxSy0pzy_K1k1KLE5NUcgtzSnJ1HULcHdUSElNKk1Pz8xLVyiuLC5JzVVIzAPKp5Zk5KfwMLCmJeYUp_JCaW4GRTfXEGcP3dSC_PjU4oLE5NS81JJ4Zz9DQzMzMyNDc1NHY2LUAAD6iyxS</recordid><startdate>20230829</startdate><enddate>20230829</enddate><creator>ZHOU DONGLAI</creator><creator>WANG JING</creator><creator>HU CONG</creator><creator>ZHU ZHENG</creator><creator>YANG ZHENJIA</creator><creator>ZHENG FEI</creator><creator>ZUO WENCUI</creator><scope>EVB</scope></search><sort><creationdate>20230829</creationdate><title>Network-based multi-FPGA debugging system and method</title><author>ZHOU DONGLAI ; WANG JING ; HU CONG ; ZHU ZHENG ; YANG ZHENJIA ; ZHENG FEI ; ZUO WENCUI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN116662175A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>ZHOU DONGLAI</creatorcontrib><creatorcontrib>WANG JING</creatorcontrib><creatorcontrib>HU CONG</creatorcontrib><creatorcontrib>ZHU ZHENG</creatorcontrib><creatorcontrib>YANG ZHENJIA</creatorcontrib><creatorcontrib>ZHENG FEI</creatorcontrib><creatorcontrib>ZUO WENCUI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ZHOU DONGLAI</au><au>WANG JING</au><au>HU CONG</au><au>ZHU ZHENG</au><au>YANG ZHENJIA</au><au>ZHENG FEI</au><au>ZUO WENCUI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Network-based multi-FPGA debugging system and method</title><date>2023-08-29</date><risdate>2023</risdate><abstract>The invention relates to a network-based multi-FPGA (Field Programmable Gate Array) debugging system, which comprises a PC (Personal Computer) end, server software, a network switch and a plurality of FPGA boards with network ports, according to the method, a traditional field debugging method for the target FPGA board system is networked, so that debugging personnel can remotely debug and maintain the target FPGA board-level system through the Internet, the development and debugging efficiency is improved, and the maintenance cost is reduced. Program programming and debugging are carried out by adopting a network cable or an optical fiber, the limitation of the length of a JTAG cable is broken through, the JTAG cable needs to be connected with a PC, a special working scene can be applicable only by connecting a network and a network switch, the method is simple and low in maintenance cost, point-to-point debugging and analysis are supported, and many-to-many batch debugging and analysis are also supported. A</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
title | Network-based multi-FPGA debugging system and method |
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