Fault testing method and circuit

The invention provides a method and a circuit for testing faults. The invention provides a circuit for testing faults of an integrated clock gating (ICG) unit, and the circuit comprises a trigger, an input clock signal of the trigger is the output of the ICG unit, wherein the flip-flop receives an inverted phase of an output of the flip-flop as an input data signal and determines, based on the output of the flip-flop, whether an enable network of the ICG unit has a fixed at zero fault. According to the embodiment of the invention, the fault test of the enabling network of the ICG can be completed, and the jump fault test can be completed by means of the ICG unit. 本发明提供测试故障的方法及电路。其中本发明提供的一种测试集成时钟门控(ICG)单元的故障的电路，该电路包括：触发器，其中该触发器的输入时钟信号是该ICG单元的输出，其中该触发器接收该触发器的输出的反相作为输入数据信号并基于该触发器的输出确定该ICG单元的使能网络是否具有固定在0故障。本发明实施例可完成对ICG的使能网络的故障测试及可借助ICG单元完成跳变故障测试。