Delayed communication over synchronous interface

A chiplet system may include a serial peripheral interface (SPI) bus for communication. A primary device coupled to the SPI bus may generate read or write instructions for a secondary device. In response to an instruction from the primary device, the secondary device may prepare for a response. The response message may include a secondary device status field for indicating that the secondary device is ready to provide a particular data payload to the primary device. Using a delay communicated from the secondary device to the primary device may enable SPI operations with longer latency to proceed without exclusively occupying the SPI bus. 一种小芯片系统可包含用于通信的串行外围接口(SPI)总线。耦合到所述SPI总线的主要装置可生成用于次要装置的读取或写入指令。响应于来自所述主要装置的指令，所述次要装置可准备响应。响应消息可包含用于指示所述次要装置准备好将特定数据有效负载提供到所述主要装置的次要装置状态字段。使用从所述次要装置传达到所述主要装置的延迟可使时延较长的SPI操作能够在不独占所述SPI总线的情况下继续进行。