SOC chip layout optimization method and device

The invention discloses an SOC chip layout optimization method and device, and the method comprises the steps: determining the specification parameters and the module shape of a test module based on an initial netlist of a target chip, and building the test module which accords with the specification parameters and the module shape; determining layout information of a standard unit on the test module under different layout schemes according to the winding parameters of the same winding on the target chip; standard units utilizing different layout schemes are established on the test module in combination with the layout information; simulating different path delay values on the target chip by using the standard units of different layout schemes on the test module; and optimizing and adjusting the layout plan of the target chip according to the winding information meeting the path delay condition in different path delay values. According to the method, path delay information support is provided for planning of