Frequency division clock phase synchronization method, circuit and electronic device

The invention provides a method for performing frequency division clock phase synchronization in a multi-frequency division clock system, a related synchronous control circuit, a synchronous control sub-circuit and an electronic device. The method may include: performing a frequency division operation according to a source clock to generate a first frequency-divided clock and a second frequency-divided clock; performing phase relation detection on the first frequency division clock according to the second frequency division clock to generate a phase relation detection result signal; performing a logic operation on a first phase selection result output signal and the phase relation detection result signal to generate a second phase selection result output signal; and outputting one of the second frequency division clock and an inverted signal of the second frequency division clock according to the second phase selection result output signal for further use by a physical layer circuit. 本发明提供一种用来在一多分频时钟系统中进行分频时钟