Data control circuit and memory device

A data control circuit includes a first latch circuit, a self-resistance circuit, a second latch circuit, a third latch circuit, a first data timing mark signal generating circuit, and a second data timing mark signal generating circuit. The first latch circuit is configured to receive a data window signal. The self-resistance circuit is coupled to the first latch circuit and is used for generating a protection signal. The second latch circuit is coupled to the self-resistance circuit and is used for outputting a first data time sequence mark signal. The third latch circuit is coupled to the second latch circuit and is used for outputting a second data time sequence mark signal. The first data time sequence mark signal generating circuit is used for generating a third data time sequence mark signal. The second data time sequence mark signal generating circuit is used for generating a fourth data time sequence mark signal. 一种数据控制电路包含有第一锁存器电路、自阻电路、第二锁存器电路、第三锁存器电路、第一数据时序标记信号产生电路以及第二数据时序标记信号产生电路。第一锁存器电路用以接收数据窗信号。