Data processing architecture of high-precision radar signal operation chip and operation chip system

The invention discloses a data processing architecture of a high-precision radar signal operation chip. The data processing architecture comprises a plurality of PE units and a plurality of super computing units which are connected into an array, a divider and a root divider are integrated in the super computing unit; the PE unit comprises a single-precision floating point summator, a multiplier, data selectors MUX0-MUX2, a D trigger, single-precision floating point data ports A, B, C, D, E, S and M and PE function control ports M0-M2 for controlling the MUX0-MUX2; the PE unit realizes a real number operation function through different configuration modes of ports M0-M2, and realizes a complex number operation function through combination of different numbers of PE units at different positions in the array and different configuration of operation modes. According to the method, high-speed floating-point real number or complex number basic operation can be realized, and the method has common radar algorithms a