Low-cost low-power-consumption adder

The invention provides a low-cost and low-power-consumption summator which comprises a low-bit group output summation circuit which adopts a serial summator with low cost, low power consumption and high time delay to replace a selective carry summator with high cost, high power consumption and low time delay to obtain low-bit group output summation. The high-order group output summation circuit obtains the high-order group output summation by adopting a low-delay selection carry adder, so that the key path delay of the high-order group output summation and the key path delay of the low-order group output summation are at the same level, and the final working speed of the adder is not influenced. On the premise that the maximum delay or the speed of the adder is kept unchanged, the serial adder is adopted to replace a selective carry adder in a low-order group, so that the cost and the power consumption of the adder can be further reduced. 本发明提供一种低成本低功耗加法器，包括低位组输出求和电路采用成本小、功耗低、延时高的串行加法器代替成本高、功耗高、延时低的选择进位加法器获得低