Layout patterns for static random access memory

The invention provides a layout pattern of a static random access memory. The device at least comprises a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	GUO YOUCE, HUANG LIPING, CHEN JIANHONG, WANG SHURU, ZENG JUNYAN, HUANG JUNXIAN
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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