Layout patterns for static random access memory

The invention provides a layout pattern of a static random access memory. The device at least comprises a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) which are arranged on the substrate, the PD2A and the PD2B are mutually connected in parallel, the plurality of gate structures comprise a first J-shaped gate structure, and the first J-shaped gate structure is an integrated structure. 本发明提供一种静态随机存取存储器的布局图案，至少包含一PU1(第一上拉晶体管)、一PU2(第二上拉晶体管)、一PD1A(第一下拉晶体管)、一PD1B(第二下拉晶体管)、一PD2A(第三下拉晶体管)、一PD2B(第四下拉晶体管)、一PG1A(第一存取晶体管)、一PG1B(第二存取晶体管)、一PG2A(第三存取晶体管)、一PG2B(第四存取晶体管)位于该基底上，其中该PD1A与该PD1B相互并联，该PD2A与该PD2B相互并联，其中该多个栅极结构中包含有一第一J状栅极结构，且该第一J状栅极结构为一体成形的结构。