Interleaved and vertically spaced integrated circuit line metallization with different vias and metal selective deposition

Adjacent interconnect lines are in staggered and vertically spaced locations, which correspondingly reduces their capacitive coupling within one level of interconnect metallization. The short and high interconnect via openings land on vertically staggered interconnect lines. A selectively deposited cap material on an upper one of the interleaved interconnect lines limits over-etching of the short vias such that the high vias advance toward a lower one of the interleaved interconnect lines. Via openings of different depths may be filled, for example, with a single damascene metallization process, defining a coplanar top surface for all via metallizations over interleaved and vertically spaced-apart interconnect lines. 相邻互连线处于交错的并且垂直间隔开的位置，这相应减小了其在互连金属化的一个层级之内的电容耦合。矮的和高的互连过孔开口着陆于垂直交错的互连线上。在交错互连线中的上方互连线上选择性沉积的帽盖材料限制了矮过孔的过刻蚀，而使得高过孔朝向交错互连线中的下方互连线前进。不同深度的过孔开口可以例如利用单镶嵌金属化工艺填充，为交错的并且垂直间隔开的互连线上方的所有过孔金属化限定共面顶表面。