Digital chip layout wiring global optimization method and system

The invention discloses a digital chip layout and wiring global optimization method and system, and the method comprises the steps: carrying out the abstract modeling of a three-dimensional chip layout and wiring problem, and respectively building a basic mathematical model of a layout sub-problem and a wiring sub-problem; carrying out local search by adopting a secondary assignment algorithm, and solving an initial layout of a standard element in each unit to obtain a relaxation solution of a layout sub-problem; the initial layout is adjusted through a tabu search algorithm and neighborhood actions based on unit exchange, a global layout is generated, and a legal solution of a layout sub-problem is obtained; performing global wiring by iteratively calling a single network wiring algorithm to generate a Steiner forest relaxation solution, and performing rewiring or adjustment and repair on a network violating constraints to obtain an initial layout wiring solution; and on the basis of the initial layout wirin