Scan flip-flop and scan chain
The invention discloses a scan flip-flop and a scan chain. The scan flip-flop comprises a normal data establishing circuit and a second transmission gate. Wherein the normal data establishing circuit comprises a first phase inverter, a first transmission gate, a second phase inverter and a third pha...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention discloses a scan flip-flop and a scan chain. The scan flip-flop comprises a normal data establishing circuit and a second transmission gate. Wherein the normal data establishing circuit comprises a first phase inverter, a first transmission gate, a second phase inverter and a third phase inverter; the first control end of the first transmission gate is suitable for accessing a first transmission gate control signal; a second control end of the first transmission gate is suitable for accessing a logic inverse signal of a control signal of the first transmission gate; the first transmission gate is suitable for being switched on when the trigger edge of the clock signal is a rising edge and the clock signal and the scanning enable signal are both in low level and switched off when at least one of the clock signal and the scanning enable signal is in high level; and when the trigger edge of the clock signal is a falling edge, turning on when the clock signal is at a high level and the scanning enab |
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