Processor with multiple extraction and decoding pipelines

A processor [100] employs a plurality of fetch and decode pipelines [112, 113] by dividing an instruction stream [101] into instruction blocks having identified boundaries. The processor includes a branch predictor [102] that generates a branch prediction. Each branch prediction corresponds to a branch instruction and includes a prediction that the corresponding branch is to be taken or not taken. In addition, each branch prediction identifies both an end of the current branch prediction window and a start of another branch prediction window. Using the known boundaries, the processor provides different sequential fetch streams [115, 116] to different ones of the plurality of fetch and decode pipelines that simultaneously process instructions of the different fetch streams, thereby improving the total instruction throughput at the processor. 本发明涉及一种处理器[100]，其通过将指令流[101]划分成具有所标识边界的指令块而采用多个提取和解码管线[112,113]。该处理器包括生成分支预测的分支预测器[102]。每个分支预测对应于分支指令并且包括对应的分支将被采用或不被采用的预测。另外，每个分支预测标识当前分支预测窗口的结束和另一个分支预测窗口的开始两者。使用这些已知边界，该