Preparation method of 3D heterogeneous chip, 3D heterogeneous chip and attenuator
The invention provides a preparation method of a 3D heterogeneous chip, the 3D heterogeneous chip and an attenuator. The preparation method comprises the following steps: obtaining a first IC chip, wherein the first IC chip is a III-V group compound semiconductor chip; preparing a first metal shield...
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| creator | WANG LEI DAI JIAN WANG JIE YANG YUFENG CHENG ZEPU WANG SHUPENG SU CHENFEI LIANG JIACHENG GAO XIAN YAO ZHIHONG WU SHIYING LIU HAIFENG SHEN JINGXUAN HAN YUPENG LIU LELE |
| description | The invention provides a preparation method of a 3D heterogeneous chip, the 3D heterogeneous chip and an attenuator. The preparation method comprises the following steps: obtaining a first IC chip, wherein the first IC chip is a III-V group compound semiconductor chip; preparing a first metal shielding layer at a first preset position on the lower surface of the first IC chip; obtaining a second IC chip, wherein the second IC chip is a Si-based complementary metal oxide semiconductor chip; preparing a second metal shielding layer at a second preset position on the lower surface of the second IC chip; connecting the lower surface of the second IC chip with the upper surface of the first IC chip to obtain a 3D heterogeneous chip; wherein when the lower surface of the second IC chip is connected with the upper surface of the first IC chip, the first preset position corresponds to the second preset position up and down. According to the invention, the on-chip spatial isolation of the 3D heterogeneous chip can be |
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The preparation method comprises the following steps: obtaining a first IC chip, wherein the first IC chip is a III-V group compound semiconductor chip; preparing a first metal shielding layer at a first preset position on the lower surface of the first IC chip; obtaining a second IC chip, wherein the second IC chip is a Si-based complementary metal oxide semiconductor chip; preparing a second metal shielding layer at a second preset position on the lower surface of the second IC chip; connecting the lower surface of the second IC chip with the upper surface of the first IC chip to obtain a 3D heterogeneous chip; wherein when the lower surface of the second IC chip is connected with the upper surface of the first IC chip, the first preset position corresponds to the second preset position up and down. According to the invention, the on-chip spatial isolation of the 3D heterogeneous chip can be</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS ; RESONATORS ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230623&DB=EPODOC&CC=CN&NR=116313836A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230623&DB=EPODOC&CC=CN&NR=116313836A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WANG LEI</creatorcontrib><creatorcontrib>DAI JIAN</creatorcontrib><creatorcontrib>WANG JIE</creatorcontrib><creatorcontrib>YANG YUFENG</creatorcontrib><creatorcontrib>CHENG ZEPU</creatorcontrib><creatorcontrib>WANG SHUPENG</creatorcontrib><creatorcontrib>SU CHENFEI</creatorcontrib><creatorcontrib>LIANG JIACHENG</creatorcontrib><creatorcontrib>GAO XIAN</creatorcontrib><creatorcontrib>YAO ZHIHONG</creatorcontrib><creatorcontrib>WU SHIYING</creatorcontrib><creatorcontrib>LIU HAIFENG</creatorcontrib><creatorcontrib>SHEN JINGXUAN</creatorcontrib><creatorcontrib>HAN YUPENG</creatorcontrib><creatorcontrib>LIU LELE</creatorcontrib><title>Preparation method of 3D heterogeneous chip, 3D heterogeneous chip and attenuator</title><description>The invention provides a preparation method of a 3D heterogeneous chip, the 3D heterogeneous chip and an attenuator. The preparation method comprises the following steps: obtaining a first IC chip, wherein the first IC chip is a III-V group compound semiconductor chip; preparing a first metal shielding layer at a first preset position on the lower surface of the first IC chip; obtaining a second IC chip, wherein the second IC chip is a Si-based complementary metal oxide semiconductor chip; preparing a second metal shielding layer at a second preset position on the lower surface of the second IC chip; connecting the lower surface of the second IC chip with the upper surface of the first IC chip to obtain a 3D heterogeneous chip; wherein when the lower surface of the second IC chip is connected with the upper surface of the first IC chip, the first preset position corresponds to the second preset position up and down. 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| subjects | BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS RESONATORS SEMICONDUCTOR DEVICES |
| title | Preparation method of 3D heterogeneous chip, 3D heterogeneous chip and attenuator |
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