Preparation method of 3D heterogeneous chip, 3D heterogeneous chip and attenuator

The invention provides a preparation method of a 3D heterogeneous chip, the 3D heterogeneous chip and an attenuator. The preparation method comprises the following steps: obtaining a first IC chip, wherein the first IC chip is a III-V group compound semiconductor chip; preparing a first metal shielding layer at a first preset position on the lower surface of the first IC chip; obtaining a second IC chip, wherein the second IC chip is a Si-based complementary metal oxide semiconductor chip; preparing a second metal shielding layer at a second preset position on the lower surface of the second IC chip; connecting the lower surface of the second IC chip with the upper surface of the first IC chip to obtain a 3D heterogeneous chip; wherein when the lower surface of the second IC chip is connected with the upper surface of the first IC chip, the first preset position corresponds to the second preset position up and down. According to the invention, the on-chip spatial isolation of the 3D heterogeneous chip can be