Layout of semiconductor memory device

The invention discloses a layout of a semiconductor memory device. The layout comprises a substrate and a ternary content addressable memory. The ternary content addressable memory is arranged on the substrate and comprises a plurality of ternary content addressable memory bit cells, at least two of the ternary content addressable memory bit cells are in mirror symmetry along an axis of symmetry, and each ternary content addressable memory bit cell comprises two memory cells electrically connected to two word lines respectively. And a logic circuit electrically connected to the memory cells. The logic circuit includes two first read transistors, and two second read transistors, each second read transistor including a gate and two source/drain regions, the source/drain regions of the second read transistors being electrically connected to the two match lines and the first read transistors, respectively, in which word lines are disposed in parallel between the match lines. 本发明公开一种半导体存储装置的布局，包括基底以及三元内容可寻址存储器。三元内