Parallelization decoding device and method under high-speed serial interface clock-line-free application

The invention relates to a parallel decoding device and method for a high-speed serial interface without a clock line, and relates to the field of FPGA (Field Programmable Gate Array) chip application. The device comprises a data receiving and processing module, a data sending module and a local clock module. The data receiving and processing module comprises an over-sampling sub-module, a parallel receiving sub-module and a decoding sub-module which are connected in sequence; the data sending module comprises an OSERDES sub-module and a differential output sub-module. The local clock module comprises a PLL module. According to the device, an oversampling method is combined with phase adjustment of the clock module, collection and unified decoding of eight-path phase data are achieved, parallel-serial conversion of the data is carried out through the sending module, and finally parallel decoding with high stability and serial data output are combined. Under the condition of no cable corresponding to the clock