Ultra-low power consumption full CMOS (Complementary Metal-Oxide-Semiconductor Transistor) current reference source adopting bias lining technology and leakage isolation

The invention discloses an ultra-low power consumption full CMOS (Complementary Metal-Oxide-Semiconductor Transistor) current reference source adopting a bias lining technology and leakage isolation, which mainly comprises four parts, namely a specific current output stage, a leakage isolator, a biasing circuit and a secondary linear voltage regulator. Wherein the specific current output stage adopts a bias lining technology and a cascode structure, so that the power consumption, the output precision and the load regulation rate are all improved; the leakage isolator isolates the substrate leakage current introduced by the isolation substrate bias; the bias circuit is used for generating a bias voltage inversely proportional to the temperature and performing temperature compensation on the output stage; the two-stage linear voltage regulator generates a power supply voltage irrelevant to the power supply voltage by using two-stage voltage reference, so that the power supply linearity of the reference current