Layout patterns for static random access memory

A layout pattern of a static random access memory (SRAM) includes a substrate on which a PL1 (first pull-up transistor), a PD1 (first pull-down transistor), a PL2 (second pull-up transistor) and a PD2 (second pull-down transistor) are located, and also includes a PG1A (first access transistor), a PB1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor), the PG1A and the PG1B include the same first fin-shaped structure, and the PG1B and the PG1B include the same second fin-shaped structure. The PG1A, the PG1B, the PG2A and the PG2B comprise the same second fin-shaped structures, the first local interconnection layer is located between the PG1A and the PG1B and located on the fin-shaped structures contained in the PL1 and the PD1, and the second local interconnection layer is located between the PG2A and the PG2B and located on the fin-shaped structures contained in the PL2 and the PD2. 一种静态随机存取存储器(static random-access memory，SRAM)的布局图案，包含基底、PL1(第一上拉晶体管)、PD1(第一下拉晶体