Chip and packaging method

The embodiment of the invention discloses a chip and a packaging method thereof. In the chip, each first welding pad on a first welding pad array on a first substrate is attached to each corresponding second pin in a second pin array on different bare chips, so that short-distance and high-density interconnection between the different bare chips is realized. And the plastic package body is used for wrapping the first pin, the second pin, the first welding pad and the first substrate, so that the fan-out unit and the first substrate are plastically packaged into an integral structure. In the integral structure, the bottom of each first pin of the first pin array used for being electrically connected with the periphery of the chip on the bare chip is not wrapped by the plastic package body, so that each first pin can be directly and electrically connected to the periphery of the chip. The overall size of the chip provided by the embodiment of the invention mainly depends on the sizes of the plurality of bare ch