Integrated chip and method of forming integrated chip

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a dielectric structure disposed on the substrate; a plurality of conductive interconnect layers disposed within the dielectric structure, where the plurality of conductive interconnect layers includes alternating layers of interconnect wires and interconnect vias; and a metal-insulator-metal (MIM) capacitor disposed within the dielectric structure and including a lower conductive electrode separated from the upper conductive electrode by a capacitor dielectric structure wherein the metal-insulator-metal capacitor extends vertically through two or more of the plurality of conductive interconnect layers, the metal-insulator-metal capacitor includes a plurality of protrusions extending outwardly from a lower surface of the upper conductive electrode, where the plurality of protrusions are disposed back at a non-zero distance from an outermost sidewall of the upper conductive electrode. The embodiment of the in