Timing precision maintenance for reduced power consumption during system sleep

Embodiments of the present disclosure provide systems and methods for maintaining timing accuracy in different modes of operation of a device, such as a wireless node. The timing circuit may switch the clock signal between two different modes (e.g., high power and low power) while maintaining timing...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: VANACKER BERTRAND, G. W. WU, LEMKIN MARK A
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Embodiments of the present disclosure provide systems and methods for maintaining timing accuracy in different modes of operation of a device, such as a wireless node. The timing circuit may switch the clock signal between two different modes (e.g., high power and low power) while maintaining timing accuracy. In the high power mode, the timing circuit may provide a high frequency clock signal, while in the low power mode it may provide a low frequency clock signal. In addition, switching between different clock signals can be synchronized to a selection edge of a low frequency clock signal. 本公开的实施例提供了用于在设备(例如无线节点)的不同操作模式中保持定时精度的系统和方法。定时电路可以在两种不同模式(例如,高功率和低功率)之间切换时钟信号,同时保持定时精度。在高功率模式中,定时电路可以提供高频时钟信号,而在低功率模式中它可以提供低频时钟信号。此外,可以同步不同时钟信号之间的切换到低频时钟信号的选择边缘。