Hardware accelerator, electronic device and device for neural network

A hardware accelerator, an electronic device, and a device for a neural network are provided. A hardware accelerator, the hardware accelerator comprising: a comparator; an XNOR gate; an accumulator; the basic block of the neural network comprises a first batch normalization layer, a quantization layer, a convolution layer, an activation layer and a second batch normalization layer, and wherein the quantization layer and the convolution layer correspond to the first batch normalization layer, the quantization layer, the activation layer and the second batch normalization layer. The base block is driven by means of a combination of a first batch normalization operation, a sign function operation, a shift convolution operation, an activation function operation, a second batch normalization operation, and a residual join operation. 提供硬件加速器、电子装置和用于神经网络的装置。一种硬件加速器，所述硬件加速器包括：比较器；同或(XNOR)门；累加器；以及乘法和累加(MAC)运算器，其中，神经网络的基本块包括：第一批量归一化层、量化层、卷积层、激活层和第二批量归一化层，并且其中，基本块由通过第一批量归一化运算、符号函数运算、移位卷积运算、激活函数运算、第二批量归一化运算和残差连接操作的组合的装置驱