Resource occupancy rate optimization method of FPGA convolution accelerator

The invention belongs to the technical field of hardware accelerators, and discloses a resource occupancy rate optimization method of an FPGA (Field Programmable Gate Array) convolution accelerator, which comprises the following steps of: firstly, carrying out configurable logic block level optimization on two aspects of a lookup table and a carry chain aiming at a radix-4booth multiplier in the convolution accelerator so as to reduce LUT (Look Up Table) resource required for realizing a single multiplier; then, a method for merging partial products is designed according to the optimized multiplier, and multiplication and addition are carried out by neglecting an intermediate result, so that LUT resources are further saved. Compared with a traditional method, the performance of the method is equivalent to that of a design using an approximate multiplier on the premise of no precision loss. And meanwhile, the requirement of deploying a large number of convolution processing units on the FPGA under the conditio