Chip low-power-consumption enable control circuit
The invention provides a low-power-consumption enable control circuit for a chip. The low-power-consumption enable control circuit comprises a PMOS (P-channel Metal Oxide Semiconductor) tube MP0, an NMOS (N-channel Metal Oxide Semiconductor) tube MN0, a resistor R2, a resistor R3, a resistor R4, a Z...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention provides a low-power-consumption enable control circuit for a chip. The low-power-consumption enable control circuit comprises a PMOS (P-channel Metal Oxide Semiconductor) tube MP0, an NMOS (N-channel Metal Oxide Semiconductor) tube MN0, a resistor R2, a resistor R3, a resistor R4, a Zener tube D1, a Zener tube D2 and a bias current generating circuit, one end of the resistor R2 is connected with an enabling end EN of the chip, the other end of the resistor R2 is connected with a grid electrode of the PMOS tube MP0 and an anode of the Zener tube D1, a drain electrode of the PMOS tube MP0 is grounded, a cathode of the Zener tube D1 is connected with a source electrode of the PMOS tube MP0, a cathode of the Zener tube D2, one end of the resistor R3 and a grid electrode of the NMOS tube MN0, a drain electrode of the NMOS tube MN0 is connected with one end of the resistor R4, the other end of the resistor R3 and the other end of the resistor R4 are connected with a power supply VCC, and the other en |
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