General convolutional neural network accelerator implementation method based on FPGA

The invention relates to the field of deep learning and embedded machine vision, in particular to an FPGA (field programmable gate array)-based universal convolutional neural network accelerator implementation method, which comprises a processor system and a programmable logic, a hardware platform adopts a ZYNQ series FPGA of XILINX, a control algorithm is designed on the processor system side of the FPGA, and the processor system side of the FPGA is connected with the programmable logic. An RTL convolutional neural network accelerator IP is designed on the programmable logic side of an FPGA, a hardware system comprises a camera and a VGA interface, an image collected by the camera is recognized, and a result is output to an external screen through the VGA interface. According to the method, fine-grained optimization is carried out according to FPGA resources, and under the condition that the precision meets the requirement, a large amount of resources are saved, the forward reasoning speed of the convolution