Chip testing system and chip testing method

The invention relates to a chip test system and a chip test method, and the method comprises the steps: dividing a to-be-tested chip into a time sequence unit and a non-time sequence unit, connecting the ends of the same attribute in the units of the same type in parallel, and then connecting the ends to the output end of the corresponding attribute on a test vector output module; therefore, the test vector required by the full-function test of the combinational logic function of the non-time sequence unit and/or the time sequence logic function of the time sequence unit in the chip to be tested can be configured. During testing, the control function of the controller is utilized to control the test vector output module to output a test vector according to a preset rule, and the test vector output module outputs the test vector according to the number of output paths of a single tested unit which is connected with the input end of the selected output circuit and acted by the current test vector. The control s